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ARD2
Post-R03
Airbag Reference Demonstrator using MPC5604P
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ARD2
Post-R03
Airbag Reference Demonstrator using MPC5604P
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00001 /****************************************************************************** 00002 * 00003 * Freescale Semiconductor Inc. 00004 * (c) Copyright 2004-2008 Freescale Semiconductor, Inc. 00005 * (c) Copyright 2001-2004 Motorola, Inc. 00006 * ALL RIGHTS RESERVED. 00007 * 00008 * =================================================================== * 00009 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY * 00010 * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * 00011 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * 00012 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL FREESCALE OR * 00013 * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * 00014 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * 00015 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * 00016 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * 00017 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * 00018 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * 00019 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * 00020 * OF THE POSSIBILITY OF SUCH DAMAGE. * 00021 * =================================================================== * 00022 * 00023 ***************************************************************************/ 00042 #ifndef MY_TYPES_H 00043 #define MY_TYPES_H 00044 00045 #include "derivative.h" 00046 00047 // SPI instruction description 00048 /* binary code module page 00049 #define READ_DEV_ID 0b00000000//READ_DEV_ID read device identifier 0000000 IM: SPI 67 00050 #define READ_REV_ID 0b00000110//READ_REV_ID read revision identifier 0000011 IM: SPI 67 00051 #define READ_MON_ID 0b00000010//READ_MON_ID read monitored identifier 0000001 SAM 118 00052 #define WD2_TRIGGER 0b00001000//WD2_TRIGGER trigger watchdog 2 0000100 SAM 114 00053 #define WD3_TRIGGER 0b00001010//WD3_TRIGGER trigger watchdog 3 0000101 SAM 114 00054 #define READ_WD_STATUS 0b00000100//READ_WD_STATUS read watchdog status 0000010 SAM 114 00055 #define READ_WD_FC 0b00001110//READ_WD_FC read watchdog fault counter 0000111 SAM 114 00056 #define EOP 0b00001100//EOP end of programming 0000110 SAM 67 00057 #define PSI_SUPPLY 0b00010000//PSI_SUPPLY switch PSI supply on/off 0001000 IM: PSI 80 00058 #define FLM_STATUS 0b00010010//FLM_STATUS read FLM status 0001001 FLM 55 00059 #define END_ENABLE 0b00010100//END_ENABLE end enable time 0001010 SAM 125 00060 #define SET_I_AIO 0b00010110//SET_I_AIO set AIO current 0001011 IM: AIO 98 00061 #define READ_THRES 0b00011000//READ_THRES read last threshold used 0001100 SAM 122 00062 #define SET_I_LIN 0b00011010//SET_I_LIN set LIN current 0001101 IM: LIN 89 00063 #define START_ADC 0b00011100//START_ADC start A/D conversion 0001110 SAM 102 00064 #define READ_ADC 0b00011110//READ_ADC read result of A/D conversion 0001111 SAM 102 00065 #define TEST_ANA_HEAD 0b00100000//TEST_ANA_HEAD test analog head 0010000 SAM 102 00066 #define POWER_CTRL 0b00100010//POWER_CTRL control power 0010001 POM 37 00067 #define POWER_STATUS 0b00100100//POWER_STATUS read power status 0010010 POM 37 00068 #define AOUT_CTRL 0b00100110//AOUT_CTRL control AOUT multiplexer and output 0010011 IM: AOUT 106 00069 #define HS_ON1_4 0b00101000//HS_ON1_4 switch on/off highside loop 1 – 4 0010100 FLM 45 00070 #define HS_ON5_8 0b00101010//HS_ON5_8 switch on/off highside loop 5 – 8 0010101 FLM 45 00071 #define HS_ON9_12 0b00101100//HS_ON9_12 switch on/off highside loop 9 – 12 0010110 FLM 45 00072 #define FLM_TEST_SRC 0b00101110//FLM_TEST_SRC control firing loop test current source 0010111 FLM 55 00073 #define LS_ON1_4 0b00110000//LS_ON1_4 switch on/off lowside loop 1 – 4 0011000 FLM 49 00074 #define LS_ON5_8 0b00110010//LS_ON5_8 switch on/off lowside loop 5 – 8 0011001 FLM 49 00075 #define LS_ON9_12 0b00110100//LS_ON9_12 switch on/off lowside loop 9 – 12 0011010 FLM 49 00076 #define FLM_TEST_SINK 0b00110110//FLM_TEST_SINK control firing loop test current sink 0011011 FLM 55 00077 #define FLM_LOCK 0b00111010//FLM_LOCK lock/unlock firing loops 0011101 FLM 61 00078 #define FLM_LOWLEAK 0b00111100//FLM_LOWLEAK control low leakage measurements 0011110 FLM 55 00079 #define FIRE_COUNTER 0b00111110//FIRE_COUNTER read firing loop counter 0011111 FLM 45 00080 #define READ_PSI 0b10000000//READ_PSI read PSI data / select read channel 1000000 IM: PSI 80 00081 #define SELECT_PSI 0b11000010//SELECT_PSI select PSI channel for read access 1100001 IM: PSI 80 00082 #define DISPOSAL 0b11000100//DISPOSAL control disposal functionality 1100010 SAM 133 00083 #define SET_AIO_PWM 0b11111110//SET_AIO_PWM set AIO PWM mode and frequency 1111111 IM: AIO 98 00084 #define DEMAND_TEST 0b00111000//DEMAND_TEST demand for test 0011100 SAM 122 00085 #define THRES_TEST_DATA 0b11001000//THRES_TEST_DATA set threshold test data 1100100 SAM 122 00086 #define THRES_TEST_SID 0b11001010//THRES_TEST_SID set threshold test safety identifier 1100101 SAM 122 00087 #define ENABLE_PROG 0b11001100//ENABLE_PROG enable programming 1100110 SAM 67 00088 #define SET_MM5_MODE 0b11001110//SET_MM5_MODE set/reset MM5 mode 1100111 SAM 118 00089 #define PSI_SYNC_GEN 0b11110010//PSI_SYNC_GEN generate PSI sync pulse 1111001 IM: PSI 82 00090 #define PSI_SYNC_MASK 0b11110100//PSI_SYNC_MASK set PSI sync pulse mask 1111010 IM: PSI 82 00091 #define AIO_STATUS 0b11111000//AIO_STATUS read AIO status 1111100 IM: AIO 98 00092 #define SET_PSI_IPP 0b11011010//SET_PSI_IPP set PSI push / pull current 1101101 IM: PSI 82 00093 #define READ_PSI_IPP 0b11010010//READ_PSI_IPP read PSI push / pull current 1101001 IM: PSI 82 00094 #define PSI_IQ_STATUS 0b11010100//PSI_IQ_STATUS read PSI quiescent cur. control status 1101010 IM: PSI 82 00095 #define CLEAR_FIRE_CNT 0b11010110//CLEAR_FIRE_CNT clear all firing current counters 1101011 FLM 45 00096 #define SID_EVALUATE 0b11011000//SID_EVALUATE trigger SID evaluation 1101100 SAM 122 00097 #define TEST_PSI_CONS 0b11011100//TEST_PSI_CONS test PSI data path consistency 1101110 IM:PSI 80 00098 */ 00099 00100 //Table 5: general SPI instructions 00101 00102 //SPI instruction description 00103 00104 /* binary code module page 00105 #define PROG_GENERAL 0b01000000//PROG_GENERAL program general settings 0100000 SAM 128 00106 #define PROG_UP_THRES 0b01000010//PROG_UP_THRES program upper threshold of switch evaluation 0100001 SAM 128 00107 #define PROG_LOW_THRES 0b01000100//PROG_LOW_THRES program lower threshold of switch evaluation 0100010 SAM 128 00108 #define PROG_AIN1_2 0b01001000//PROG_AIN1_2 program AIN current of channel 1 – 2 0100100 IM: AIN 96 00109 #define PROG_AIN3_4 0b01001010//PROG_AIN3_4 program AIN current of channel 3 – 4 0100101 IM: AIN 96 00110 #define PROG_AIN5_6 0b01001100//PROG_AIN5_6 program AIN current of channel 5 – 6 0100110 IM: AIN 96 00111 #define PROG_AIO_WL 0b01111000//PROG_AIO_WL program AIO warning lamp mode 0111100 SAM 98 00112 #define PROG_PSI1_LINE 0b01001110//PROG_PSI1_LINE program PSI channel 1 0100111 IM: PSI 80 00113 #define PROG_PSI2_LINE 0b01010000//PROG_PSI2_LINE program PSI channel 2 0101000 IM: PSI 80 00114 #define PROG_PSI3_LINE 0b01010010//PROG_PSI3_LINE program PSI channel 3 0101001 IM: PSI 80 00115 #define PROG_PSI4_LINE 0b01010100//PROG_PSI4_LINE program PSI channel 4 0101010 IM: PSI 80 00116 #define PROG_UFS_THRES 0b01010110//PROG_UFS_THRES program threshold for up-front sensor 0101011 SAM 122 00117 #define PROG_PAS_THRES 0b01011000//PROG_PAS_THRES program threshold for PAS sensor 0101100 SAM 122 00118 #define PROG_PRES_THRES 0b01011010//PROG_PRES_THRES program threshold for pressure sensor 0101101 SAM 122 00119 #define PROG_ROLL_THRES 0b01011100//PROG_ROLL_THRES program threshold for roll-rate sensor 0101110 SAM 122 00120 #define PROG_X_THRES 0b01011110//PROG_X_THRES program threshold for central x-direction sensor 0101111 SAM 122 00121 #define PROG_Y_THRES 0b01100000//PROG_Y_THRES program threshold for central y-direction sensor 0110000 SAM 122 00122 #define PROG_POWER 0b01100010//PROG_POWER program power control 0110001 POM 37 00123 #define PROG_FLM_ENH 0b01100100//PROG_FLM_ENH program enhanced FLM mode 0110010 FLM 45 00124 #define PROG_SDIS1_4 0b01100110//PROG_SDIS1_4 program special disable function of firing loop 1 – 4 0110011 FLM 59 00125 #define PROG_SDIS5_8 0b01101000//PROG_SDIS5_8 program special disable function of firing loop 5 – 8 0110100 FLM 59 00126 #define PROG_SDIS9_12 0b01101010//PROG_SDIS9_12 program special disable function of firing loop 9 – 12 0110101 FLM 59 00127 #define PROG_DISXY1_4 0b01101100//PROG_DISXY1_4 program x-/y-disable function of firing loop 1 – 4 0110110 FLM 59 00128 #define PROG_DISXY5_8 0b01101110//PROG_DISXY5_8 program x-/y-disable function of firing loop 5 – 8 0110111 FLM 59 00129 #define PROG_DISXY9_12 0b01110000//PROG_DISXY9_12 program x-/y-disable function of firing loop 9 – 12 0111000 FLM 59 00130 #define PROG_FLM_CONF 0b01110010//PROG_FLM_CONF program general firing loop configuration 0111001 FLM 45 00131 #define PROG_PSYNC_MODE 0b01110100//PROG_PSYNC_MODE program PSI sync mode 0111010 IM: PSI 82 00132 #define PROG_SDIS_CH 0b01111010//PROG_SDIS_CH program special disable channel 0111101 SAM 128 00133 #define PROG_PSI_SID 0b01110110//PROG_PSI_SID program PSI safety identifier 0111011 IM: PSI 82 00134 #define PROG_MM5_SID 0b01111110//PROG_MM5_SID program MM5 safety identifier 0111111 SAM 118 00135 #define PROG_ENH_SAFETY 0b01000110//PROG_ENH_SAFETY program enhanced safety mode 0100011 SAM 132 00136 00137 */ 00138 00139 //Table 6: SPI programming instructions 00140 00141 // SPI instruction description binary code module page 00142 /*#define READ_DEV_ID 0b00000000//READ_DEV_ID read device identifier 0000000 SAM 67 00143 #define DEMAND_TEST 0b00111000//DEMAND_TEST demand for test 0011100 SAM 118 00144 #define READ_SENSOR 0b1xxx0000//READ_SENSOR read sensor data 1xxx000 SAM 118 00145 */ 00146 00147 //ADJUST #define MM5_READ_ACC1 0b011001101//MM5_READ_ACC1 read MM5 acceleration data channel 1 011001101 SAM 116 00148 //ADJUST #define MM5_READ_ACC2 0b011001101//MM5_READ_ACC2 read MM5 acceleration data channel 2 011001110 SAM 116 00149 //ADJUST #define MM5_READ_GYRO 0b011001111//MM5_READ_GYRO read MM5 gyro data 011001111 SAM 116 00150 //Table 7: Monitor SPI instructions 00151 00152 00153 // Oroya registers // Type Fuse SPI PSI5 Ref. 00154 #define SN0 0x00 // 00 $0 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0] // F R1W1 R2W3 R4 4.2.1 00155 #define SN1 0x01 // 01 $1 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8] // F R1W1 R2W3 R4 4.2.1 00156 #define SN2 0x02 // 02 $2 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] SN[18] SN[17] SN[16] // F R1W1 R2W3 R4 4.2.1 00157 #define SN3 0x03 // 03 $3 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24] // F R1W1 R2W3 R4 4.2.1 00158 #define DEVCFG1 0x04 // 04 $4 DEVCFG1 SYNC_PM OC_FILT[1] OC_FILT[0] POLARITY AXIS RNG[2] RNG[1] RNG[0] // F R1W1 R2W3 R4 4.2.2 00159 #define DEVCFG2 0x05 // 05 $5 DEVCFG2 LOCK_C PCM SYNC_PD LATENCY DATASIZE BLANKTIME P_CRC BAUD // C/F R1W1 R2W3 R4W3 4.2.3 00160 #define DEVCFG3 0x06 // 06 $6 DEVCFG3 TRANS_MD[1] TRANS_MD[0] LPFSEL[1] LPFSEL[0] TS_2[9] TS_2[8] TS_1[9] TS_1[8] // C/F R1W1 R2W3 R4W3 4.2.3 00161 #define DEVCFG4 0x07 // 07 $7 DEVCFG4 TS_1[7] TS_1[6] TS_1[5] TS_1[4] TS_1[3] TS_1[2] TS_1[1] TS_1[0] // C/F R1W1 R2W3 R4W3 4.2.3 00162 #define DEVCFG5 0x08 // 08 $8 DEVCFG5 TS_2[7] TS_2[6] TS_2[5] TS_2[4] TS_2[3] TS_2[2] TS_2[1] TS_2[0] // C/F R1W1 R2W3 R4W3 4.2.3 00163 #define DEVCFG6 0x09 // 09 $9 CD00 INIT2_EXT ASYNC C_DIR[1] C_DIR[0] C_REV[3] C_REV[2] C_REV[1] C_REV[0] // C/F R1W1 R2W3 R4W3 4.2.4 00164 #define DEVCFG7 0x0A // 10 $0A CD01 M[3] M[2] M[1] M[0] Y[3] Y[2] Y[1] Y[0] // C/F R1W1 R2W3 R4W3 4.2.4 00165 #define DEVCFG8 0x0B // 11 $0B CD02 CRC_C[2] CRC_C[1] CRC_C[0] D[4] D[3] D[2] D[1] D[0] // C/F R1W1 R2W3 R4W3 4.2.4 00166 #define SC 0x0C // 12 $0C SC 0 DPM_B Reserved IDEN_B OC_INIT_B IDEF_B OFF_B TEMP_B // D - R R 4.2.5 00167 #define REG13 0x0D // 13 $0D - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved // - - - - - 00168 #define CRC_F 0x0E // 14 $0E CRC_F Reserved Reserved Reserved Reserved LOCK_F CRC_F[2] CRC_F[1] CRC_F[0] // F R1W1 R2W3 R2 4.2.6 00169 #define VREG 0x0F // 15 $0F VREG Reserved VBUF_CCT VDDA_CCT VDD_CCT Reserved Reserved VREGA_DIS VREG_DIS // F R1W1 R2W3 R2 4.2.7 00170 #define V_REFREG 0x10 // 16 $10 V_REFREG VREF[3] VREF[2] VREF[1] VREF[0] Reserved VREG[2] VREG[1] VREG[0] // F R1W1 R2W3 R2 4.2.7 00171 #define I_REF 0x11 // 17 $11 I_REF Reserved IMOD_SLOWSLEW IMOD_TRIM[1] IMOD_TRIM[0] IMOD_IDLE IREF[2] IREF[1] IREF[0] // F R1W1 R2W3 R2 4.2.7 00172 #define MOD_TRIM 0x12 // 18 $12 MOD_TRIM Reserved Reserved LG HG MTRIM[3] MTRIM[2] MTRIM[1] MTRIM[0] // F R1W1 R2W3 R2 4.2.8 00173 #define OVERTEMP 0x13 // 19 $13 OVERTEMP OTD Reserved Reserved OTT[4] OTT[3] OTT[2] OTT[1] OTT[0] // F R1W1 R2W3 R2 4.2.9 00174 #define OFFLPF_TH 0x14 // 20 $14 OFFLPF_TH Reserved Reserved Reserved Reserved Reserved Reserved OFFTH[1] OFFTH[0] // F R1W1 R2W3 R2 4.2.10 00175 #define SELFT_TH 0x15 // 21 $15 SELFT_TH Reserved Reserved Reserved Reserved Reserved Reserved ST_TH[1] ST_TH[0] // F R1W1 R2W3 R2 4.2.11 00176 #define SELFT_ATRIM 0x16 // 22 $16 SELFT_ATRIM Reserved STT[6] STT[5] STT[4] STT[3] STT[2] STT[1] STT[0] // F R1W1 R2W3 R2 4.2.12 00177 #define OSC_ATRIM 0x17 // 23 $17 OSC_ATRIM Reserved Reserved OSCT[5] OSCT[4] OSCT[3] OSCT[2] OSCT[1] OSCT[0] // F R1W1 R2W3 R2 4.2.13 00178 #define TRIM_C0L 0x18 // 24 $18 TRIM_C0L C0[7] C0[6] C0[5] C0[4] C0[3] C0[2] C0[1] C0[0] // F R1W1 R2W3 R2 4.2.14 00179 #define TRIM_C0H 0x19 // 25 $19 TRIM_C0H Reserved Reserved Reserved Reserved C0[11] C0[10] C0[9] C0[8] // F R1W1 R2W3 R2 4.2.14 00180 #define TRIM_C1L 0x1A // 26 $1A TRIM_C1L C1[7] C1[6] C1[5] C1[4] C1[3] C1[2] C1[1] C1[0] // F R1W1 R2W3 R2 4.2.14 00181 #define TRIM_C1H 0x1B // 27 $1B TRIM_C1H Reserved Reserved Reserved Reserved C1[11] C1[10] C1[9] C1[8] // F R1W1 R2W3 R2 4.2.14 00182 #define TRIM_C2L 0x1C // 28 $1C TRIM_C2L C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0] // F R1W1 R2W3 R2 4.2.14 00183 #define TRIM_C2H 0x1D // 29 $1D TRIM_C2H Reserved Reserved Reserved Reserved C2[11] C2[10] C2[9] C2[8] // F R1W1 R2W3 R2 4.2.14 00184 #define TRIM_DL 0x1E // 30 $1E TRIM_DL D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] // F R1W1 R2W3 R2 4.2.14 00185 #define TRIM_DH 0x1F // 31 $1F TRIM_DH Reserved Reserved Reserved Reserved D[11] D[10] D[9] D[8] // F R1W1 R2W3 R2 4.2.14 00186 #define TRIM_EL 0x20 // 32 $20 TRIM_EL E[7] E[6] E[5] E[4] E[3] E[2] E[1] E[0] // F R1W1 R2W3 R2 4.2.14 00187 #define TRIM_EH 0x21 // 33 $21 TRIM_EH Reserved Reserved Reserved Reserved E[11] E[10] E[9] E[8] // F R1W1 R2W3 R2 4.2.14 00188 #define TRIM_FL 0x22 // 34 $22 TRIM_FL F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0] // F R1W1 R2W3 R2 4.2.14 00189 #define TRIM_FH 0x23 // 35 $23 TRIM_FH Reserved Reserved Reserved Reserved F[11] F[10] F[9] F[8] // F R1W1 R2W3 R2 4.2.14 00190 #define TEMP_OC 0x24 // 36 $24 TEMP_OC 1 TEMP_OC[6] TEMP_OC[5] TEMP_OC[4] TEMP_OC[3] TEMP_OC[2] TEMP_OC[1] TEMP_OC[0] // F R1W1 R2W3 R2 4.2.15 00191 #define DSP_CTL 0x25 // 37 $25 DSP_CTL Reserved Reserved Reserved Reserved LIMITB OUT_INV SINC_INV HPFB // F R1W1 R2W3 R2 4.2.16 00192 #define FS_OTP0L 0x26 // 38 $26 FS_OTP0L FS_OTP0[7] FS_OTP0[6] FS_OTP0[5] FS_OTP0[4] FS_OTP0[3] FS_OTP0[2] FS_OTP0[1] FS_OTP0[0] // F R1W1 R2W3 R2 4.2.17 00193 #define FS_OTP0H 0x27 // 39 $27 FS_OTP0H FS_OTP0[15] FS_OTP0[14] FS_OTP0[13] FS_OTP0[12] FS_OTP0[11] FS_OTP0[10] FS_OTP0[9] FS_OTP0[8] // F R1W1 R2W3 R2 4.2.17 00194 #define FS_OTP1L 0x28 // 40 $28 FS_OTP1L FS_OTP1[7] FS_OTP1[6] FS_OTP1[5] FS_OTP1[4] FS_OTP1[3] FS_OTP1[2] FS_OTP1[1] FS_OTP1[0] // F R1W1 R2W3 R2 4.2.17 00195 #define FS_OTP1H 0x29 // 41 $29 FS_OTP1H FS_OTP1[15] FS_OTP1[14] FS_OTP1[13] FS_OTP1[12] FS_OTP1[11] FS_OTP1[10] FS_OTP1[9] FS_OTP1[8] // F R1W1 R2W3 R2 4.2.17 00196 #define FS_OTP2L 0x2A // 42 $2A FS_OTP2L FS_OTP2[7] FS_OTP2[6] FS_OTP2[5] FS_OTP2[4] FS_OTP2[3] FS_OTP2[2] FS_OTP2[1] FS_OTP2[0] // F R1W1 R2W3 R2 4.2.17 00197 #define FS_OTP2H 0x2B // 43 $2B FS_OTP2H FS_OTP2[15] FS_OTP2[14] FS_OTP2[13] FS_OTP2[12] FS_OTP2[11] FS_OTP2[10] FS_OTP2[9] FS_OTP2[8] // F R1W1 R2W3 R2 4.2.17 00198 #define FS_OTP3L 0x2C // 44 $2C FS_OTP3L FS_OTP3[7] FS_OTP3[6] FS_OTP3[5] FS_OTP3[4] FS_OTP3[3] FS_OTP3[2] FS_OTP3[1] FS_OTP3[0] // F R1W1 R2W3 R2 4.2.17 00199 #define FS_OTP3H 0x2D // 45 $2D FS_OTP3H FS_OTP3[15] FS_OTP3[14] FS_OTP3[13] FS_OTP3[12] FS_OTP3[11] FS_OTP3[10] FS_OTP3[9] FS_OTP3[8] // F R1W1 R2W3 R2 4.2.17 00200 #define F_ID 0x2E // 46 $2E F_ID FID[7] FID[6] FID[5] FID[4] FID[3] FID[2] FID[1] FID[0] // F R1W1 R2W3 R2 4.2.18 00201 #define PSI5_CTL 0x2F // 47 $2F PSI5_CTL PSI5_DMEN PSI5_STEB PSI5_C[5] PSI5_C[4] PSI5_C[3] PSI5_C[2] PSI5_C[1] PSI5_C[0] // F R1W1 R2W3 R2 4.2.19 00202 #define OTP_SPARE 0x30 // 48 $30 OTP_SPARE OTP_SPR[7] OTP_SPR[6] OTP_SPR[5] OTP_SPR[4] OTP_SPR[3] OTP_SPR[2] OTP_SPR[1] OTP_SPR[0] // F R1W1 R2W3 R2 4.2.20 00203 #define REG49 0x31 // 49 $31 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved // - - - - - 00204 #define REG50 0x32 // 50 $32 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved // - - - - - 00205 #define REG51 0x33 // 51 $33 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved // - - - - - 00206 #define REG52 0x34 // 52 $34 - Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved // - - - - - 00207 #define DATA_SPARE 0x35 // 53 $35 DATA_SPARE DATASPR[7] DATASPR[6] DATASPR[5] DATASPR[4] DATASPR[3] DATASPR[2] DATASPR[1] DATASPR[0] // D - R2W2 R2W2 4.2.21 00208 #define DSP_D0 0x36 // 54 $36 DSP_D0 DSP_D[7] DSP_D[6] DSP_D[5] DSP_D[4] DSP_D[3] DSP_D[2] DSP_D[1] DSP_D[0] // D - R2 R2 4.2.22 00209 #define DSP_D1 0x37 // 55 $37 DSP_D1 DSP_D[15] DSP_D[14] DSP_D[13] DSP_D[12] DSP_D[11] DSP_D[10] DSP_D[9] DSP_D[8] // D - R2 R2 4.2.22 00210 #define DSP_D2 0x38 // 56 $38 DSP_D2 DSP_D[23] DSP_D[22] DSP_D[21] DSP_D[20] DSP_D[19] DSP_D[18] DSP_D[17] DSP_D[16] // D - R2 R2 4.2.22 00211 #define DSP_D3 0x39 // 57 $39 DSP_D3 Reserved Reserved Reserved Reserved Reserved Reserved DSP_D[25] DSP_D[24] // D - R2 R2 4.2.22 00212 #define ACC_DL 0x3A // 58 $3A ACC_DL ACC[7] ACC[6] ACC[5] ACC[4] ACC[3] ACC[2] ACC[1] ACC[0] // D - R2 R2 4.2.23 00213 #define ACC_DH 0x3B // 59 $3B ACC_DH ACC[15] ACC[14] ACC[13] ACC[12] ACC[11] ACC[10] ACC[9] ACC[8] // D - R2 R2 4.2.23 00214 #define TEMP_DL 0x3C // 60 $3C TEMP_DL TEMP[7] TEMP[6] TEMP[5] TEMP[4] TEMP[3] TEMP[2] TEMP[1] TEMP[0] // D - R2 R2 4.2.24 00215 #define TEMP_DH 0x3D // 61 $3D TEMP_DH Reserved Reserved Reserved Reserved Reserved Reserved TEMP[9] TEMP[8] // D - R2 R2 4.2.24 00216 #define DEV_STAT0 0x3E // 62 $3E DEV_STAT0 DEVINIT TEMP_ERR ST_ERR REG_WERR ST_EN DPM_SPI DM_PSI5 PM_PSI5 // D - R2 R2 4.2.25 00217 #define DEV_STAT1 0x3F // 63 $3F DEV_STAT1 TEST_STAT BSW_STAT DPM_TM Reserved Reserved Reserved Reserved DSP_OVFL // D - R2 R2 4.2.25 00218 #define FUSE_STAT 0x40 // 64 $40 FUSE_STAT FVCC_UV FUSE_ERR ARD_DONE RW_DONE RD_OP WR_OP Reserved Reserved // D - R2 R2 4.2.26 00219 #define DEV_CTL0 0x41 // 65 $41 DEV_CTL0 DSPOP_DIS FVCC_DIS OFFOUT_SEL DOUT_SCB INTPOLB Reserved TRIMB LPFB // D - R2W2 R2W2 4.2.27 00220 #define DEV_CTL1 0x42 // 66 $42 DEV_CTL1 Reserved Reserved Reserved Reserved DM_SDATA Reserved DIN_SEL[1] DIN_SEL[0] // D - R2W2 R2W2 4.2.27 00221 #define DEV_CTL2 0x43 // 67 $43 DEV_CTL2 Reserved Reserved Reserved Reserved Reserved D_SEL[2] D_SEL[1] D_SEL[0] // D - R2W2 R2W2 4.2.27 00222 #define FUSE_PROGC 0x44 // 68 $44 FUSE_PROGC Reserved PTIME[2] PTIME[1] PTIME[0] Reserved PCTL[2] PCTL[1] PCTL[0] // D - R2W2 R2W5 4.2.28 00223 #define ALOG_CTL0 0x45 // 69 $45 ALOG_CTL0 IMOD_DIS MOD_DIS Reserved VDAC_SEL CAPTEST Reserved Reserved VBUF_DIS // D - R2W2 R2W2 4.2.29 00224 #define ALOG_CTL1 0x46 // 70 $46 ALOG_CTL1 Reserved Reserved Reserved Reserved Reserved FUSE_I[2] FUSE_I[1] FUSE_I[0] // D - R2W2 R2W2 4.2.29 00225 #define ALOG_CTL2 0x47 // 71 $47 ALOG_CTL2 SYNCLPFOFF SYNCLPFRST INT_HIZ Reserved Reserved Reserved Reserved MOD_AMUXEN // D - R2W2 R2W2 4.2.29 00226 #define PCM_CTL 0x48 // 72 $48 PCM_CTL Reserved Reserved PCM_MUX[5] PCM_MUX[4] PCM_MUX[3] PCM_MUX[2] PCM_MUX[1] PCM_MUX[0] // D - R2W2 R2W2 4.2.30 00227 #define TEST_CTL 0x49 // 73 $49 TEST_CTL Reserved Reserved TEST_MUX[5] TEST_MUX[4] TEST_MUX[3] TEST_MUX[2] TEST_MUX[1] TEST_MUX[0] // D - R2W2 R2W2 4.2.31 00228 #define BSW_CTL 0x4A // 74 $4A BSW_CTL Reserved Reserved Reserved BSW_MUX[4] BSW_MUX[3] BSW_MUX[2] BSW_MUX[1] BSW_MUX[0] // D - R2W2 R2W2 4.2.32 00229 #define DOUT_CTL 0x4B // 75 $4B DOUT_CTL Reserved Reserved Reserved Reserved Reserved DO_MUX[2] DO_MUX[1] DO_MUX[0] // D - R2W2 R2W2 4.2.33 00230 #define ID_NUM 0x4C // 76 $4C ID_NUM ID_NUM[7] ID_NUM[6] ID_NUM[5] ID_NUM[4] ID_NUM[3] ID_NUM[2] ID_NUM[1] ID_NUM[0] // D - R2 R2 4.2.34 00231 #define SCAN_MODE 0x4D // 77 $4D SCAN_MODE Reserved Reserved Reserved Reserved Reserved Reserved IDDQ SCANM // D - R2W2 - 4.2.35 00232 #define SOFT_RESET 0x4E // 78 $4E SOFT_RESET Reserved Reserved Reserved Reserved Reserved Reserved SRST[1] SRST[0] // D - R2W2 - 4.2.36 00233 // 1.Access is either automatically initiated during initialization time or done by FUSE_PROGC write command. 00234 // 2.Access is allowed in SPI DPM and PSI5 DM. 00235 // 3.Access is allowed in SPI DPM and PSI5 PM unless the corresponding lock bit is set. 00236 // 4.Access is allowed in SPI DPM, PSI5 PM and PSI5 DM. 00237 // 5.A PSI5 PM specific command flags the digital block to update these register bits and initiate automatic fuse programming. 00238 // TYPE: F : freescale OTP bit, C : Customer OTP bit, D : Digital block register bit. 00239 00240 // Read Register / Display when using debugger 00241 typedef union { 00242 uint16_t word; 00243 struct { 00244 uint16_t DEVID0 :1; 00245 uint16_t DEVID1 :1; 00246 uint16_t DEVID2 :1; 00247 uint16_t DEVID3 :1; 00248 uint16_t DEVID4 :1; 00249 uint16_t DEVID5 :1; 00250 uint16_t DEVID6 :1; 00251 uint16_t DEVID7 :1; 00252 uint16_t ST_DIS1 :1; 00253 uint16_t ST_DIS2 :1; 00254 uint16_t ST_WDF :1; 00255 uint16_t ST_BSY :1; 00256 uint16_t ST_0 :1; 00257 uint16_t ST_EOP :1; 00258 uint16_t ST_TST :1; 00259 uint16_t ST_TFF :1; 00260 } Bits; 00261 struct { 00262 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00263 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00264 } MergedBits; 00265 } READ_DEVID; 00266 00267 typedef union { 00268 uint16_t word; 00269 struct { 00270 uint16_t MASKREV0 :1; 00271 uint16_t MASKREV1 :1; 00272 uint16_t MASKREV2 :1; 00273 uint16_t MASKREV3 :1; 00274 uint16_t SWREV4 :1; 00275 uint16_t SWREV5 :1; 00276 uint16_t SWREV6 :1; 00277 uint16_t SWREV7 :1; 00278 uint16_t ST_DIS1 :1; 00279 uint16_t ST_DIS2 :1; 00280 uint16_t ST_WDF :1; 00281 uint16_t ST_BSY :1; 00282 uint16_t ST_0 :1; 00283 uint16_t ST_EOP :1; 00284 uint16_t ST_TST :1; 00285 uint16_t ST_TFF :1; 00286 } Bits; 00287 struct { 00288 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00289 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00290 } MergedBits; 00291 } READ_REVID; 00292 00293 typedef union { 00294 uint16_t word; 00295 struct { 00296 uint16_t monitored_id0 :1; 00297 uint16_t monitored_id1 :1; 00298 uint16_t monitored_id2 :1; 00299 uint16_t monitored_id3 :1; 00300 uint16_t monitored_id4 :1; 00301 uint16_t monitored_id5 :1; 00302 uint16_t monitored_id6 :1; 00303 uint16_t monitored_id7 :1; 00304 uint16_t ST_DIS1 :1; 00305 uint16_t ST_DIS2 :1; 00306 uint16_t ST_WDF :1; 00307 uint16_t ST_BSY :1; 00308 uint16_t ST_0 :1; 00309 uint16_t ST_EOP :1; 00310 uint16_t ST_TST :1; 00311 uint16_t ST_TFF :1; 00312 } Bits; 00313 struct { 00314 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00315 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00316 } MergedBits; 00317 } READ_MONID; 00318 00319 typedef union { 00320 uint16_t word; 00321 struct { 00322 uint16_t wd2_checkword0 :1; 00323 uint16_t wd2_checkword1 :1; 00324 uint16_t wd2_checkword2 :1; 00325 uint16_t wd2_checkword3 :1; 00326 uint16_t wd2_checkword4 :1; 00327 uint16_t wd2_checkword5 :1; 00328 uint16_t wd2_checkword6 :1; 00329 uint16_t wd2_checkword7 :1; 00330 uint16_t ST_DIS1 :1; 00331 uint16_t ST_DIS2 :1; 00332 uint16_t ST_WDF :1; 00333 uint16_t ST_BSY :1; 00334 uint16_t ST_0 :1; 00335 uint16_t ST_EOP :1; 00336 uint16_t ST_TST :1; 00337 uint16_t ST_TFF :1; 00338 } Bits; 00339 struct { 00340 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00341 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00342 } MergedBits; 00343 } WD2TRIGGER; 00344 00345 typedef union { 00346 uint16_t word; 00347 struct { 00348 uint16_t wd3_checkword0 :1; 00349 uint16_t wd3_checkword1 :1; 00350 uint16_t wd3_checkword2 :1; 00351 uint16_t wd3_checkword3 :1; 00352 uint16_t wd3_checkword4 :1; 00353 uint16_t wd3_checkword5 :1; 00354 uint16_t wd3_checkword6 :1; 00355 uint16_t wd3_checkword7 :1; 00356 uint16_t ST_DIS1 :1; 00357 uint16_t ST_DIS2 :1; 00358 uint16_t ST_WDF :1; 00359 uint16_t ST_BSY :1; 00360 uint16_t ST_0 :1; 00361 uint16_t ST_EOP :1; 00362 uint16_t ST_TST :1; 00363 uint16_t ST_TFF :1; 00364 } Bits; 00365 struct { 00366 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00367 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00368 } MergedBits; 00369 } WD3TRIGGER; 00370 00371 typedef union { 00372 uint16_t word; 00373 struct { 00374 uint16_t wd1_underflow :1; 00375 uint16_t wd1_overflow :1; 00376 uint16_t wd2_underflow :1; 00377 uint16_t wd2_overflow :1; 00378 uint16_t wd2_badresponse :1; 00379 uint16_t wd3_overflow :1; 00380 uint16_t wd3_badresponse :1; 00381 uint16_t fault_count :1; 00382 uint16_t ST_DIS1 :1; 00383 uint16_t ST_DIS2 :1; 00384 uint16_t ST_WDF :1; 00385 uint16_t ST_BSY :1; 00386 uint16_t ST_0 :1; 00387 uint16_t ST_EOP :1; 00388 uint16_t ST_TST :1; 00389 uint16_t ST_TFF :1; 00390 } Bits; 00391 struct { 00392 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00393 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00394 } MergedBits; 00395 } READ_WDSTATUS; 00396 00397 typedef union { 00398 uint16_t word; 00399 struct { 00400 uint16_t fault_counter0 :1; 00401 uint16_t fault_counter1 :1; 00402 uint16_t WD1_flag :1; 00403 uint16_t WD2_flag :1; 00404 uint16_t WD3_flag :1; 00405 uint16_t res_conf :1; 00406 uint16_t wd_reset :1; 00407 uint16_t por :1; 00408 uint16_t ST_DIS1 :1; 00409 uint16_t ST_DIS2 :1; 00410 uint16_t ST_WDF :1; 00411 uint16_t ST_BSY :1; 00412 uint16_t ST_0 :1; 00413 uint16_t ST_EOP :1; 00414 uint16_t ST_TST :1; 00415 uint16_t ST_TFF :1; 00416 } Bits; 00417 struct { 00418 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00419 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00420 } MergedBits; 00421 } READ_WDFC; 00422 00423 typedef union { 00424 uint16_t word; 00425 struct { 00426 uint16_t EOP1 :1; 00427 uint16_t EOP2 :1; 00428 uint16_t TM :1; 00429 uint16_t Bit3 :1; 00430 uint16_t Bit4 :1; 00431 uint16_t Bit5 :1; 00432 uint16_t Bit6 :1; 00433 uint16_t Bit7 :1; 00434 uint16_t ST_DIS1 :1; 00435 uint16_t ST_DIS2 :1; 00436 uint16_t ST_WDF :1; 00437 uint16_t ST_BSY :1; 00438 uint16_t ST_0 :1; 00439 uint16_t ST_EOP :1; 00440 uint16_t ST_TST :1; 00441 uint16_t ST_TFF :1; 00442 } Bits; 00443 struct { 00444 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00445 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00446 } MergedBits; 00447 } READ_EOP; 00448 00449 typedef union { 00450 uint16_t word; 00451 struct { 00452 uint16_t LEV0 :1; 00453 uint16_t LEV1 :1; 00454 uint16_t LEV2 :1; 00455 uint16_t LEV3 :1; 00456 uint16_t Bit4 :1; 00457 uint16_t Bit5 :1; 00458 uint16_t Bit6 :1; 00459 uint16_t Bit7 :1; 00460 uint16_t ST_DIS1 :1; 00461 uint16_t ST_DIS2 :1; 00462 uint16_t ST_WDF :1; 00463 uint16_t ST_BSY :1; 00464 uint16_t ST_0 :1; 00465 uint16_t ST_EOP :1; 00466 uint16_t ST_TST :1; 00467 uint16_t ST_TFF :1; 00468 } Bits; 00469 struct { 00470 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00471 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00472 } MergedBits; 00473 } PSISUPPLY; 00474 00475 typedef union { 00476 uint16_t word; 00477 struct { 00478 uint16_t UL_HS :1; 00479 uint16_t UL_LS :1; 00480 uint16_t DIS_AHP_HIS :1; 00481 uint16_t EN_FL :1; 00482 uint16_t Bit4 :1; 00483 uint16_t Bit5 :1; 00484 uint16_t Bit6 :1; 00485 uint16_t Bit7 :1; 00486 uint16_t ST_DIS1 :1; 00487 uint16_t ST_DIS2 :1; 00488 uint16_t ST_WDF :1; 00489 uint16_t ST_BSY :1; 00490 uint16_t ST_0 :1; 00491 uint16_t ST_EOP :1; 00492 uint16_t ST_TST :1; 00493 uint16_t ST_TFF :1; 00494 } Bits; 00495 struct { 00496 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00497 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00498 } MergedBits; 00499 } FLMSTATUS; 00500 00501 typedef union { 00502 uint16_t word; 00503 struct { 00504 uint16_t Bit0 :1; 00505 uint16_t DIS_Y :1; 00506 uint16_t DIS_X :1; 00507 uint16_t DIS_S :1; 00508 uint16_t DIS_AHP :1; 00509 uint16_t DIS_ALP :1; 00510 uint16_t Bit6 :1; 00511 uint16_t Bit7 :1; 00512 uint16_t ST_DIS1 :1; 00513 uint16_t ST_DIS2 :1; 00514 uint16_t ST_WDF :1; 00515 uint16_t ST_BSY :1; 00516 uint16_t ST_0 :1; 00517 uint16_t ST_EOP :1; 00518 uint16_t ST_TST :1; 00519 uint16_t ST_TFF :1; 00520 } Bits; 00521 struct { 00522 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00523 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00524 } MergedBits; 00525 } ENDEN; 00526 00527 typedef union { 00528 uint16_t word; 00529 struct { 00530 uint16_t sid_threshold0 :1; 00531 uint16_t sid_threshold1 :1; 00532 uint16_t sid_threshold2 :1; 00533 uint16_t sid_threshold3 :1; 00534 uint16_t sid_threshold4 :1; 00535 uint16_t sid_threshold5 :1; 00536 uint16_t Bit6 :1; 00537 uint16_t Bit7 :1; 00538 uint16_t ST_DIS1 :1; 00539 uint16_t ST_DIS2 :1; 00540 uint16_t ST_WDF :1; 00541 uint16_t ST_BSY :1; 00542 uint16_t ST_0 :1; 00543 uint16_t ST_EOP :1; 00544 uint16_t ST_TST :1; 00545 uint16_t ST_TFF :1; 00546 } Bits; 00547 struct { 00548 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00549 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00550 } MergedBits; 00551 } READ_THRESHOLD; 00552 00553 typedef union { 00554 uint16_t word; 00555 struct { 00556 uint16_t Bit0 :1; 00557 uint16_t Bit1 :1; 00558 uint16_t Bit2 :1; 00559 uint16_t Bit3 :1; 00560 uint16_t Bit4 :1; 00561 uint16_t Bit5 :1; 00562 uint16_t Bit6 :1; 00563 uint16_t Bit7 :1; 00564 uint16_t ST_DIS1 :1; 00565 uint16_t ST_DIS2 :1; 00566 uint16_t ST_WDF :1; 00567 uint16_t ST_BSY :1; 00568 uint16_t ST_0 :1; 00569 uint16_t ST_EOP :1; 00570 uint16_t ST_TST :1; 00571 uint16_t ST_TFF :1; 00572 } Bits; 00573 struct { 00574 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00575 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00576 } MergedBits; 00577 } SETILIN; 00578 00579 typedef union { 00580 uint16_t word; 00581 struct { 00582 uint16_t Bit0 :1; 00583 uint16_t Bit1 :1; 00584 uint16_t Bit2 :1; 00585 uint16_t Bit3 :1; 00586 uint16_t Bit4 :1; 00587 uint16_t Bit5 :1; 00588 uint16_t Bit6 :1; 00589 uint16_t Bit7 :1; 00590 uint16_t ST_DIS1 :1; 00591 uint16_t ST_DIS2 :1; 00592 uint16_t ST_WDF :1; 00593 uint16_t ST_BSY :1; 00594 uint16_t ST_0 :1; 00595 uint16_t ST_EOP :1; 00596 uint16_t ST_TST :1; 00597 uint16_t ST_TFF :1; 00598 } Bits; 00599 struct { 00600 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00601 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00602 } MergedBits; 00603 } STARTADC; 00604 00605 typedef union { 00606 uint16_t word; 00607 struct { 00608 uint16_t ADC_result0 :1; 00609 uint16_t ADC_result1 :1; 00610 uint16_t ADC_result2 :1; 00611 uint16_t ADC_result3 :1; 00612 uint16_t ADC_result4 :1; 00613 uint16_t ADC_result5 :1; 00614 uint16_t ADC_result6 :1; 00615 uint16_t ADC_result7 :1; 00616 uint16_t ST_DIS1 :1; 00617 uint16_t ST_DIS2 :1; 00618 uint16_t ST_WDF :1; 00619 uint16_t ST_BSY :1; 00620 uint16_t ST_0 :1; 00621 uint16_t ST_EOP :1; 00622 uint16_t ST_TST :1; 00623 uint16_t ST_TFF :1; 00624 } Bits; 00625 struct { 00626 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00627 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00628 } MergedBits; 00629 } READADC; 00630 00631 typedef union { 00632 uint16_t word; 00633 struct { 00634 uint16_t Bit0 :1; 00635 uint16_t Bit1 :1; 00636 uint16_t Bit2 :1; 00637 uint16_t Bit3 :1; 00638 uint16_t Bit4 :1; 00639 uint16_t Bit5 :1; 00640 uint16_t Bit6 :1; 00641 uint16_t Bit7 :1; 00642 uint16_t ST_DIS1 :1; 00643 uint16_t ST_DIS2 :1; 00644 uint16_t ST_WDF :1; 00645 uint16_t ST_BSY :1; 00646 uint16_t ST_0 :1; 00647 uint16_t ST_EOP :1; 00648 uint16_t ST_TST :1; 00649 uint16_t ST_TFF :1; 00650 } Bits; 00651 struct { 00652 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00653 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00654 } MergedBits; 00655 } TESTANAHEAD; 00656 00657 typedef union { 00658 uint16_t word; 00659 struct { 00660 uint16_t T_EN :1; 00661 uint16_t ESR_EN :1; 00662 uint16_t CAP_EN :1; 00663 uint16_t PP_EN :1; 00664 uint16_t SLOPE :1; 00665 uint16_t Bit5 :1; 00666 uint16_t Bit6 :1; 00667 uint16_t Bit7 :1; 00668 uint16_t ST_DIS1 :1; 00669 uint16_t ST_DIS2 :1; 00670 uint16_t ST_WDF :1; 00671 uint16_t ST_BSY :1; 00672 uint16_t ST_0 :1; 00673 uint16_t ST_EOP :1; 00674 uint16_t ST_TST :1; 00675 uint16_t ST_TFF :1; 00676 } Bits; 00677 struct { 00678 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00679 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00680 } MergedBits; 00681 } POWERCTRL; 00682 00683 typedef union { 00684 uint16_t word; 00685 struct { 00686 uint16_t SL :1; 00687 uint16_t THETA :1; 00688 uint16_t VZP_G_VER :1; 00689 uint16_t VER_G_35V :1; 00690 uint16_t VER_L_12V :1; 00691 uint16_t ER33 :1; 00692 uint16_t VDN_L_8V :1; 00693 uint16_t VZP_G_18V :1; 00694 uint16_t ST_DIS1 :1; 00695 uint16_t ST_DIS2 :1; 00696 uint16_t ST_WDF :1; 00697 uint16_t ST_BSY :1; 00698 uint16_t ST_0 :1; 00699 uint16_t ST_EOP :1; 00700 uint16_t ST_TST :1; 00701 uint16_t ST_TFF :1; 00702 } Bits; 00703 struct { 00704 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00705 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00706 } MergedBits; 00707 } POWERSTATUS; 00708 00709 typedef union { 00710 uint16_t word; 00711 struct { 00712 uint16_t Bit0 :1; 00713 uint16_t Bit1 :1; 00714 uint16_t Bit2 :1; 00715 uint16_t Bit3 :1; 00716 uint16_t Bit4 :1; 00717 uint16_t Bit5 :1; 00718 uint16_t Bit6 :1; 00719 uint16_t Bit7 :1; 00720 uint16_t ST_DIS1 :1; 00721 uint16_t ST_DIS2 :1; 00722 uint16_t ST_WDF :1; 00723 uint16_t ST_BSY :1; 00724 uint16_t ST_0 :1; 00725 uint16_t ST_EOP :1; 00726 uint16_t ST_TST :1; 00727 uint16_t ST_TFF :1; 00728 } Bits; 00729 struct { 00730 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00731 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00732 } MergedBits; 00733 } AOUTCTRL; 00734 00735 typedef union { 00736 uint16_t word; 00737 struct { 00738 uint16_t hs_1_1 :1; 00739 uint16_t hs_1_2 :1; 00740 uint16_t hs_2_1 :1; 00741 uint16_t hs_2_2 :1; 00742 uint16_t hs_3_1 :1; 00743 uint16_t hs_3_2 :1; 00744 uint16_t hs_4_1 :1; 00745 uint16_t hs_4_2 :1; 00746 uint16_t ST_DIS1 :1; 00747 uint16_t ST_DIS2 :1; 00748 uint16_t ST_WDF :1; 00749 uint16_t ST_BSY :1; 00750 uint16_t ST_0 :1; 00751 uint16_t ST_EOP :1; 00752 uint16_t ST_TST :1; 00753 uint16_t ST_TFF :1; 00754 } Bits; 00755 struct { 00756 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00757 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00758 } MergedBits; 00759 } HSON14; 00760 00761 typedef union { 00762 uint16_t word; 00763 struct { 00764 uint16_t hs_5_1 :1; 00765 uint16_t hs_5_2 :1; 00766 uint16_t hs_6_1 :1; 00767 uint16_t hs_6_2 :1; 00768 uint16_t hs_7_1 :1; 00769 uint16_t hs_7_2 :1; 00770 uint16_t hs_8_1 :1; 00771 uint16_t hs_8_2 :1; 00772 uint16_t ST_DIS1 :1; 00773 uint16_t ST_DIS2 :1; 00774 uint16_t ST_WDF :1; 00775 uint16_t ST_BSY :1; 00776 uint16_t ST_0 :1; 00777 uint16_t ST_EOP :1; 00778 uint16_t ST_TST :1; 00779 uint16_t ST_TFF :1; 00780 } Bits; 00781 struct { 00782 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00783 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00784 } MergedBits; 00785 } HSON58; 00786 00787 typedef union { 00788 uint16_t word; 00789 struct { 00790 uint16_t hs_9_1 :1; 00791 uint16_t hs_9_2 :1; 00792 uint16_t hs_10_1 :1; 00793 uint16_t hs_10_2 :1; 00794 uint16_t hs_11_1 :1; 00795 uint16_t hs_11_2 :1; 00796 uint16_t hs_12_1 :1; 00797 uint16_t hs_12_2 :1; 00798 uint16_t ST_DIS1 :1; 00799 uint16_t ST_DIS2 :1; 00800 uint16_t ST_WDF :1; 00801 uint16_t ST_BSY :1; 00802 uint16_t ST_0 :1; 00803 uint16_t ST_EOP :1; 00804 uint16_t ST_TST :1; 00805 uint16_t ST_TFF :1; 00806 } Bits; 00807 struct { 00808 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00809 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00810 } MergedBits; 00811 } HSON912; 00812 00813 typedef union { 00814 uint16_t word; 00815 struct { 00816 uint16_t Bit0 :1; 00817 uint16_t Bit1 :1; 00818 uint16_t Bit2 :1; 00819 uint16_t Bit3 :1; 00820 uint16_t Bit4 :1; 00821 uint16_t Bit5 :1; 00822 uint16_t Bit6 :1; 00823 uint16_t Bit7 :1; 00824 uint16_t ST_DIS1 :1; 00825 uint16_t ST_DIS2 :1; 00826 uint16_t ST_WDF :1; 00827 uint16_t ST_BSY :1; 00828 uint16_t ST_0 :1; 00829 uint16_t ST_EOP :1; 00830 uint16_t ST_TST :1; 00831 uint16_t ST_TFF :1; 00832 } Bits; 00833 struct { 00834 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00835 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00836 } MergedBits; 00837 } FLMTESTSRC; 00838 00839 typedef union { 00840 uint16_t word; 00841 struct { 00842 uint16_t ls_1_1 :1; 00843 uint16_t ls_1_2 :1; 00844 uint16_t ls_2_1 :1; 00845 uint16_t ls_2_2 :1; 00846 uint16_t ls_3_1 :1; 00847 uint16_t ls_3_2 :1; 00848 uint16_t ls_4_1 :1; 00849 uint16_t ls_4_2 :1; 00850 uint16_t ST_DIS1 :1; 00851 uint16_t ST_DIS2 :1; 00852 uint16_t ST_WDF :1; 00853 uint16_t ST_BSY :1; 00854 uint16_t ST_0 :1; 00855 uint16_t ST_EOP :1; 00856 uint16_t ST_TST :1; 00857 uint16_t ST_TFF :1; 00858 } Bits; 00859 struct { 00860 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00861 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00862 } MergedBits; 00863 } LSON14; 00864 00865 typedef union { 00866 uint16_t word; 00867 struct { 00868 uint16_t ls_5_1 :1; 00869 uint16_t ls_5_2 :1; 00870 uint16_t ls_6_1 :1; 00871 uint16_t ls_6_2 :1; 00872 uint16_t ls_7_1 :1; 00873 uint16_t ls_7_2 :1; 00874 uint16_t ls_8_1 :1; 00875 uint16_t ls_8_2 :1; 00876 uint16_t ST_DIS1 :1; 00877 uint16_t ST_DIS2 :1; 00878 uint16_t ST_WDF :1; 00879 uint16_t ST_BSY :1; 00880 uint16_t ST_0 :1; 00881 uint16_t ST_EOP :1; 00882 uint16_t ST_TST :1; 00883 uint16_t ST_TFF :1; 00884 } Bits; 00885 struct { 00886 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00887 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00888 } MergedBits; 00889 } LSON58; 00890 00891 typedef union { 00892 uint16_t word; 00893 struct { 00894 uint16_t ls_9_1 :1; 00895 uint16_t ls_9_2 :1; 00896 uint16_t ls_10_1 :1; 00897 uint16_t ls_10_2 :1; 00898 uint16_t ls_11_1 :1; 00899 uint16_t ls_11_2 :1; 00900 uint16_t ls_12_1 :1; 00901 uint16_t ls_12_2 :1; 00902 uint16_t ST_DIS1 :1; 00903 uint16_t ST_DIS2 :1; 00904 uint16_t ST_WDF :1; 00905 uint16_t ST_BSY :1; 00906 uint16_t ST_0 :1; 00907 uint16_t ST_EOP :1; 00908 uint16_t ST_TST :1; 00909 uint16_t ST_TFF :1; 00910 } Bits; 00911 struct { 00912 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00913 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00914 } MergedBits; 00915 } LSON912; 00916 00917 typedef union { 00918 uint16_t word; 00919 struct { 00920 uint16_t Chan0 :1; 00921 uint16_t Chan1 :1; 00922 uint16_t Chan2 :1; 00923 uint16_t Chan3 :1; 00924 uint16_t Bit4 :1; 00925 uint16_t Bit5 :1; 00926 uint16_t Bit6 :1; 00927 uint16_t Bit7 :1; 00928 uint16_t ST_DIS1 :1; 00929 uint16_t ST_DIS2 :1; 00930 uint16_t ST_WDF :1; 00931 uint16_t ST_BSY :1; 00932 uint16_t ST_0 :1; 00933 uint16_t ST_EOP :1; 00934 uint16_t ST_TST :1; 00935 uint16_t ST_TFF :1; 00936 } Bits; 00937 struct { 00938 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00939 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00940 } MergedBits; 00941 } FLMTESTSINK; 00942 00943 typedef union { 00944 uint16_t word; 00945 struct { 00946 uint16_t Bit0 :1; 00947 uint16_t Bit1 :1; 00948 uint16_t Bit2 :1; 00949 uint16_t Bit3 :1; 00950 uint16_t Bit4 :1; 00951 uint16_t Bit5 :1; 00952 uint16_t Bit6 :1; 00953 uint16_t Bit7 :1; 00954 uint16_t ST_DIS1 :1; 00955 uint16_t ST_DIS2 :1; 00956 uint16_t ST_WDF :1; 00957 uint16_t ST_BSY :1; 00958 uint16_t ST_0 :1; 00959 uint16_t ST_EOP :1; 00960 uint16_t ST_TST :1; 00961 uint16_t ST_TFF :1; 00962 } Bits; 00963 struct { 00964 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00965 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00966 } MergedBits; 00967 } FLMLOCK; 00968 00969 typedef union { 00970 uint16_t word; 00971 struct { 00972 uint16_t channel0 :1; 00973 uint16_t channel1 :1; 00974 uint16_t channel2 :1; 00975 uint16_t channel3 :1; 00976 uint16_t sel :1; 00977 uint16_t Bit5 :1; 00978 uint16_t Bit6 :1; 00979 uint16_t Bit7 :1; 00980 uint16_t ST_DIS1 :1; 00981 uint16_t ST_DIS2 :1; 00982 uint16_t ST_WDF :1; 00983 uint16_t ST_BSY :1; 00984 uint16_t ST_0 :1; 00985 uint16_t ST_EOP :1; 00986 uint16_t ST_TST :1; 00987 uint16_t ST_TFF :1; 00988 } Bits; 00989 struct { 00990 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 00991 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 00992 } MergedBits; 00993 } FIRECOUNTER; 00994 00995 typedef union { 00996 uint16_t word; 00997 struct { 00998 uint16_t act_slot0 :1; 00999 uint16_t act_slot1 :1; 01000 uint16_t act_chan0 :1; 01001 uint16_t act_chan1 :1; 01002 uint16_t act_chan2 :1; 01003 uint16_t act_chan3 :1; 01004 uint16_t act_chan4 :1; 01005 uint16_t act_chan5 :1; 01006 uint16_t ST_DIS1 :1; 01007 uint16_t ST_DIS2 :1; 01008 uint16_t ST_WDF :1; 01009 uint16_t ST_BSY :1; 01010 uint16_t ST_0 :1; 01011 uint16_t ST_EOP :1; 01012 uint16_t ST_TST :1; 01013 uint16_t ST_TFF :1; 01014 } Bits; 01015 struct { 01016 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01017 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01018 } MergedBits; 01019 } READ_SELECT_PSI; 01020 01021 typedef union { 01022 uint16_t word; 01023 struct { 01024 uint16_t dis_code0 :1; 01025 uint16_t dis_code1 :1; 01026 uint16_t dis_code2 :1; 01027 uint16_t dis_code3 :1; 01028 uint16_t dis_code4 :1; 01029 uint16_t dis_code5 :1; 01030 uint16_t dis_code6 :1; 01031 uint16_t dis_code7 :1; 01032 uint16_t ST_DIS1 :1; 01033 uint16_t ST_DIS2 :1; 01034 uint16_t ST_WDF :1; 01035 uint16_t ST_BSY :1; 01036 uint16_t ST_0 :1; 01037 uint16_t ST_EOP :1; 01038 uint16_t ST_TST :1; 01039 uint16_t ST_TFF :1; 01040 } Bits; 01041 struct { 01042 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01043 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01044 } MergedBits; 01045 } READ_DISPOSAL; 01046 01047 typedef union { 01048 uint16_t word; 01049 struct { 01050 uint16_t aio1_current0 :1; 01051 uint16_t aio1_current1 :1; 01052 uint16_t aio1_current2 :1; 01053 uint16_t aio1_current3 :1; 01054 uint16_t aio2_current0 :1; 01055 uint16_t aio2_current1 :1; 01056 uint16_t aio2_current2 :1; 01057 uint16_t aio2_current3 :1; 01058 uint16_t ST_DIS1 :1; 01059 uint16_t ST_DIS2 :1; 01060 uint16_t ST_WDF :1; 01061 uint16_t ST_BSY :1; 01062 uint16_t ST_0 :1; 01063 uint16_t ST_EOP :1; 01064 uint16_t ST_TST :1; 01065 uint16_t ST_TFF :1; 01066 } Bits; 01067 struct { 01068 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01069 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01070 } MergedBits; 01071 } SETIAIO; 01072 01073 typedef union { 01074 uint16_t word; 01075 struct { 01076 uint16_t testmode0 :1; 01077 uint16_t testmode1 :1; 01078 uint16_t testmode2 :1; 01079 uint16_t testmode3 :1; 01080 uint16_t testmode4 :1; 01081 uint16_t testmode5 :1; 01082 uint16_t testmode6 :1; 01083 uint16_t testmode7 :1; 01084 uint16_t ST_DIS1 :1; 01085 uint16_t ST_DIS2 :1; 01086 uint16_t ST_WDF :1; 01087 uint16_t ST_BSY :1; 01088 uint16_t ST_0 :1; 01089 uint16_t ST_EOP :1; 01090 uint16_t ST_TST :1; 01091 uint16_t ST_TFF :1; 01092 } Bits; 01093 struct { 01094 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01095 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01096 } MergedBits; 01097 } DEMANDTEST; 01098 01099 typedef union { 01100 uint16_t word; 01101 struct { 01102 uint16_t Bit0 :1; 01103 uint16_t Bit1 :1; 01104 uint16_t Bit2 :1; 01105 uint16_t Bit3 :1; 01106 uint16_t Bit4 :1; 01107 uint16_t Bit5 :1; 01108 uint16_t Bit6 :1; 01109 uint16_t Bit7 :1; 01110 uint16_t ST_DIS1 :1; 01111 uint16_t ST_DIS2 :1; 01112 uint16_t ST_WDF :1; 01113 uint16_t ST_BSY :1; 01114 uint16_t ST_0 :1; 01115 uint16_t ST_EOP :1; 01116 uint16_t ST_TST :1; 01117 uint16_t ST_TFF :1; 01118 } Bits; 01119 struct { 01120 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01121 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01122 } MergedBits; 01123 } THRESTESTDATA; 01124 01125 typedef union { 01126 uint16_t word; 01127 struct { 01128 uint16_t Bit0 :1; 01129 uint16_t Bit1 :1; 01130 uint16_t Bit2 :1; 01131 uint16_t Bit3 :1; 01132 uint16_t Bit4 :1; 01133 uint16_t Bit5 :1; 01134 uint16_t Bit6 :1; 01135 uint16_t Bit7 :1; 01136 uint16_t ST_DIS1 :1; 01137 uint16_t ST_DIS2 :1; 01138 uint16_t ST_WDF :1; 01139 uint16_t ST_BSY :1; 01140 uint16_t ST_0 :1; 01141 uint16_t ST_EOP :1; 01142 uint16_t ST_TST :1; 01143 uint16_t ST_TFF :1; 01144 } Bits; 01145 struct { 01146 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01147 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01148 } MergedBits; 01149 } THRESTESTSID; 01150 01151 typedef union { 01152 uint16_t word; 01153 struct { 01154 uint16_t en_s :1; 01155 uint16_t en_g :1; 01156 uint16_t Bit2 :1; 01157 uint16_t Bit3 :1; 01158 uint16_t Bit4 :1; 01159 uint16_t Bit5 :1; 01160 uint16_t Bit6 :1; 01161 uint16_t Bit7 :1; 01162 uint16_t ST_DIS1 :1; 01163 uint16_t ST_DIS2 :1; 01164 uint16_t ST_WDF :1; 01165 uint16_t ST_BSY :1; 01166 uint16_t ST_0 :1; 01167 uint16_t ST_EOP :1; 01168 uint16_t ST_TST :1; 01169 uint16_t ST_TFF :1; 01170 } Bits; 01171 struct { 01172 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01173 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01174 } MergedBits; 01175 } ENABLEPROG; 01176 01177 typedef union { 01178 uint16_t word; 01179 struct { 01180 uint16_t Bit0 :1; 01181 uint16_t Bit1 :1; 01182 uint16_t Bit2 :1; 01183 uint16_t Bit3 :1; 01184 uint16_t Bit4 :1; 01185 uint16_t Bit5 :1; 01186 uint16_t Bit6 :1; 01187 uint16_t Bit7 :1; 01188 uint16_t ST_DIS1 :1; 01189 uint16_t ST_DIS2 :1; 01190 uint16_t ST_WDF :1; 01191 uint16_t ST_BSY :1; 01192 uint16_t ST_0 :1; 01193 uint16_t ST_EOP :1; 01194 uint16_t ST_TST :1; 01195 uint16_t ST_TFF :1; 01196 } Bits; 01197 struct { 01198 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01199 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01200 } MergedBits; 01201 } SETMM5MODE; 01202 01203 typedef union { 01204 uint16_t word; 01205 struct { 01206 uint16_t mask_0 :1; 01207 uint16_t mask_1 :1; 01208 uint16_t mask_2 :1; 01209 uint16_t mask_3 :1; 01210 uint16_t Bit4 :1; 01211 uint16_t Bit5 :1; 01212 uint16_t Bit6 :1; 01213 uint16_t Bit7 :1; 01214 uint16_t ST_DIS1 :1; 01215 uint16_t ST_DIS2 :1; 01216 uint16_t ST_WDF :1; 01217 uint16_t ST_BSY :1; 01218 uint16_t ST_0 :1; 01219 uint16_t ST_EOP :1; 01220 uint16_t ST_TST :1; 01221 uint16_t ST_TFF :1; 01222 } Bits; 01223 struct { 01224 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01225 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01226 } MergedBits; 01227 } PSISYNCMASK; 01228 01229 typedef union { 01230 uint16_t word; 01231 struct { 01232 uint16_t current0 :1; 01233 uint16_t current1 :1; 01234 uint16_t current2 :1; 01235 uint16_t current3 :1; 01236 uint16_t pp :1; 01237 uint16_t chan0 :1; 01238 uint16_t chan1 :1; 01239 uint16_t Bit7 :1; 01240 uint16_t ST_DIS1 :1; 01241 uint16_t ST_DIS2 :1; 01242 uint16_t ST_WDF :1; 01243 uint16_t ST_BSY :1; 01244 uint16_t ST_0 :1; 01245 uint16_t ST_EOP :1; 01246 uint16_t ST_TST :1; 01247 uint16_t ST_TFF :1; 01248 } Bits; 01249 struct { 01250 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01251 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01252 } MergedBits; 01253 } SETPSIIPP; 01254 01255 typedef union { 01256 uint16_t word; 01257 struct { 01258 uint16_t i0 :1; 01259 uint16_t i1 :1; 01260 uint16_t i2 :1; 01261 uint16_t i3 :1; 01262 uint16_t Bit4 :1; 01263 uint16_t Bit5 :1; 01264 uint16_t Bit6 :1; 01265 uint16_t Bit7 :1; 01266 uint16_t ST_DIS1 :1; 01267 uint16_t ST_DIS2 :1; 01268 uint16_t ST_WDF :1; 01269 uint16_t ST_BSY :1; 01270 uint16_t ST_0 :1; 01271 uint16_t ST_EOP :1; 01272 uint16_t ST_TST :1; 01273 uint16_t ST_TFF :1; 01274 } Bits; 01275 struct { 01276 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01277 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01278 } MergedBits; 01279 } PSI5_IPP; 01280 01281 typedef union { 01282 uint16_t word; 01283 struct { 01284 uint16_t min1 :1; 01285 uint16_t max1 :1; 01286 uint16_t min2 :1; 01287 uint16_t max2 :1; 01288 uint16_t min3 :1; 01289 uint16_t max3 :1; 01290 uint16_t min4 :1; 01291 uint16_t max4 :1; 01292 uint16_t ST_DIS1 :1; 01293 uint16_t ST_DIS2 :1; 01294 uint16_t ST_WDF :1; 01295 uint16_t ST_BSY :1; 01296 uint16_t ST_0 :1; 01297 uint16_t ST_EOP :1; 01298 uint16_t ST_TST :1; 01299 uint16_t ST_TFF :1; 01300 } Bits; 01301 struct { 01302 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01303 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01304 } MergedBits; 01305 } PSIIQSTATUS; 01306 01307 01308 typedef union { 01309 uint16_t word; 01310 struct { 01311 uint16_t min1 :1; 01312 uint16_t max1 :1; 01313 uint16_t min2 :1; 01314 uint16_t max2 :1; 01315 uint16_t min3 :1; 01316 uint16_t max3 :1; 01317 uint16_t min4 :1; 01318 uint16_t max4 :1; 01319 uint16_t ST_DIS1 :1; 01320 uint16_t ST_DIS2 :1; 01321 uint16_t ST_WDF :1; 01322 uint16_t ST_BSY :1; 01323 uint16_t ST_0 :1; 01324 uint16_t ST_EOP :1; 01325 uint16_t ST_TST :1; 01326 uint16_t ST_TFF :1; 01327 } Bits; 01328 struct { 01329 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01330 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01331 } MergedBits; 01332 } TEST_PSICONS ; 01333 01334 01335 01336 01337 01338 01339 01340 01341 01342 01343 01344 typedef union { 01345 uint16_t word; 01346 struct { 01347 uint16_t ext_fire_config_14_1 :1; 01348 uint16_t ext_fire_config_14_2 :1; 01349 uint16_t ext_fire_config_14_3 :1; 01350 uint16_t ext_fire_config_58_1 :1; 01351 uint16_t ext_fire_config_58_2 :1; 01352 uint16_t ext_fire_config_58_3 :1; 01353 uint16_t Bit6 :1; 01354 uint16_t Bit7 :1; 01355 uint16_t ST_DIS1 :1; 01356 uint16_t ST_DIS2 :1; 01357 uint16_t ST_WDF :1; 01358 uint16_t ST_BSY :1; 01359 uint16_t ST_0 :1; 01360 uint16_t ST_EOP :1; 01361 uint16_t ST_TST :1; 01362 uint16_t ST_TFF :1; 01363 } Bits; 01364 struct { 01365 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01366 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01367 } MergedBits; 01368 } PROG_FLMENH; 01369 01370 typedef union { 01371 uint16_t word; 01372 struct { 01373 uint16_t S_DIS1 :1; 01374 uint16_t S_DIS2 :1; 01375 uint16_t S_DIS3 :1; 01376 uint16_t S_DIS4 :1; 01377 uint16_t Bit4 :1; 01378 uint16_t Bit5 :1; 01379 uint16_t Bit6 :1; 01380 uint16_t Bit7 :1; 01381 uint16_t ST_DIS1 :1; 01382 uint16_t ST_DIS2 :1; 01383 uint16_t ST_WDF :1; 01384 uint16_t ST_BSY :1; 01385 uint16_t ST_0 :1; 01386 uint16_t ST_EOP :1; 01387 uint16_t ST_TST :1; 01388 uint16_t ST_TFF :1; 01389 } Bits; 01390 struct { 01391 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01392 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01393 } MergedBits; 01394 } PROG_SDIS14; 01395 01396 typedef union { 01397 uint16_t word; 01398 struct { 01399 uint16_t S_DIS5 :1; 01400 uint16_t S_DIS6 :1; 01401 uint16_t S_DIS7 :1; 01402 uint16_t S_DIS8 :1; 01403 uint16_t Bit4 :1; 01404 uint16_t Bit5 :1; 01405 uint16_t Bit6 :1; 01406 uint16_t Bit7 :1; 01407 uint16_t ST_DIS1 :1; 01408 uint16_t ST_DIS2 :1; 01409 uint16_t ST_WDF :1; 01410 uint16_t ST_BSY :1; 01411 uint16_t ST_0 :1; 01412 uint16_t ST_EOP :1; 01413 uint16_t ST_TST :1; 01414 uint16_t ST_TFF :1; 01415 } Bits; 01416 struct { 01417 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01418 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01419 } MergedBits; 01420 } PROG_SDIS58; 01421 01422 typedef union { 01423 uint16_t word; 01424 struct { 01425 uint16_t S_DIS9 :1; 01426 uint16_t S_DIS10 :1; 01427 uint16_t S_DIS11 :1; 01428 uint16_t S_DIS12 :1; 01429 uint16_t Bit4 :1; 01430 uint16_t Bit5 :1; 01431 uint16_t Bit6 :1; 01432 uint16_t Bit7 :1; 01433 uint16_t ST_DIS1 :1; 01434 uint16_t ST_DIS2 :1; 01435 uint16_t ST_WDF :1; 01436 uint16_t ST_BSY :1; 01437 uint16_t ST_0 :1; 01438 uint16_t ST_EOP :1; 01439 uint16_t ST_TST :1; 01440 uint16_t ST_TFF :1; 01441 } Bits; 01442 struct { 01443 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01444 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01445 } MergedBits; 01446 } PROG_SDIS912; 01447 01448 typedef union { 01449 uint16_t word; 01450 struct { 01451 uint16_t i_test_level :1; 01452 uint16_t auto_ls :1; 01453 uint16_t auto_hs :1; 01454 uint16_t fire_mode1 :1; 01455 uint16_t fire_mode2 :1; 01456 uint16_t fire_mode3 :1; 01457 uint16_t fm58 :1; 01458 uint16_t fm14 :1; 01459 uint16_t ST_DIS1 :1; 01460 uint16_t ST_DIS2 :1; 01461 uint16_t ST_WDF :1; 01462 uint16_t ST_BSY :1; 01463 uint16_t ST_0 :1; 01464 uint16_t ST_EOP :1; 01465 uint16_t ST_TST :1; 01466 uint16_t ST_TFF :1; 01467 } Bits; 01468 struct { 01469 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01470 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01471 } MergedBits; 01472 } PROG_FLMCONF; 01473 01474 typedef union { 01475 uint16_t word; 01476 struct { 01477 uint16_t TRIG :1; 01478 uint16_t DEL :1; 01479 uint16_t ATM :1; 01480 uint16_t DA :1; 01481 uint16_t quies_reg0 :1; 01482 uint16_t quies_reg1 :1; 01483 uint16_t detec_reg0 :1; 01484 uint16_t detec_reg1 :1; 01485 uint16_t ST_DIS1 :1; 01486 uint16_t ST_DIS2 :1; 01487 uint16_t ST_WDF :1; 01488 uint16_t ST_BSY :1; 01489 uint16_t ST_0 :1; 01490 uint16_t ST_EOP :1; 01491 uint16_t ST_TST :1; 01492 uint16_t ST_TFF :1; 01493 } Bits; 01494 struct { 01495 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01496 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01497 } MergedBits; 01498 } PROG_PSYNCMODE; 01499 01500 typedef union { 01501 uint16_t word; 01502 struct { 01503 uint16_t AIN1 :1; 01504 uint16_t AIN2 :1; 01505 uint16_t AIN3 :1; 01506 uint16_t AIN4 :1; 01507 uint16_t AIN5 :1; 01508 uint16_t AIN6 :1; 01509 uint16_t AIO1 :1; 01510 uint16_t AIO2 :1; 01511 uint16_t ST_DIS1 :1; 01512 uint16_t ST_DIS2 :1; 01513 uint16_t ST_WDF :1; 01514 uint16_t ST_BSY :1; 01515 uint16_t ST_0 :1; 01516 uint16_t ST_EOP :1; 01517 uint16_t ST_TST :1; 01518 uint16_t ST_TFF :1; 01519 } Bits; 01520 struct { 01521 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01522 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01523 } MergedBits; 01524 } PROG_SDISCH; 01525 01526 typedef union { 01527 uint16_t word; 01528 struct { 01529 uint16_t AIN1 :1; 01530 uint16_t AIN2 :1; 01531 uint16_t AIN3 :1; 01532 uint16_t AIN4 :1; 01533 uint16_t AIN5 :1; 01534 uint16_t AIN6 :1; 01535 uint16_t AIO1 :1; 01536 uint16_t AIO2 :1; 01537 uint16_t ST_DIS1 :1; 01538 uint16_t ST_DIS2 :1; 01539 uint16_t ST_WDF :1; 01540 uint16_t ST_BSY :1; 01541 uint16_t ST_0 :1; 01542 uint16_t ST_EOP :1; 01543 uint16_t ST_TST :1; 01544 uint16_t ST_TFF :1; 01545 } Bits; 01546 struct { 01547 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01548 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01549 } MergedBits; 01550 } PROG_PSISID; 01551 01552 typedef union { 01553 uint16_t word; 01554 struct { 01555 uint16_t X_DIS1 :1; 01556 uint16_t X_DIS2 :1; 01557 uint16_t X_DIS3 :1; 01558 uint16_t X_DIS4 :1; 01559 uint16_t Y_DIS1 :1; 01560 uint16_t Y_DIS2 :1; 01561 uint16_t Y_DIS3 :1; 01562 uint16_t Y_DIS4 :1; 01563 uint16_t ST_DIS1 :1; 01564 uint16_t ST_DIS2 :1; 01565 uint16_t ST_WDF :1; 01566 uint16_t ST_BSY :1; 01567 uint16_t ST_0 :1; 01568 uint16_t ST_EOP :1; 01569 uint16_t ST_TST :1; 01570 uint16_t ST_TFF :1; 01571 } Bits; 01572 struct { 01573 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01574 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01575 } MergedBits; 01576 } PROG_DISXY14; 01577 01578 typedef union { 01579 uint16_t word; 01580 struct { 01581 uint16_t X_DIS5 :1; 01582 uint16_t X_DIS6 :1; 01583 uint16_t X_DIS7 :1; 01584 uint16_t X_DIS8 :1; 01585 uint16_t Y_DIS5 :1; 01586 uint16_t Y_DIS6 :1; 01587 uint16_t Y_DIS7 :1; 01588 uint16_t Y_DIS8 :1; 01589 uint16_t ST_DIS1 :1; 01590 uint16_t ST_DIS2 :1; 01591 uint16_t ST_WDF :1; 01592 uint16_t ST_BSY :1; 01593 uint16_t ST_0 :1; 01594 uint16_t ST_EOP :1; 01595 uint16_t ST_TST :1; 01596 uint16_t ST_TFF :1; 01597 } Bits; 01598 struct { 01599 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01600 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01601 } MergedBits; 01602 } PROG_DISXY58; 01603 01604 typedef union { 01605 uint16_t word; 01606 struct { 01607 uint16_t X_DIS92 :1; 01608 uint16_t X_DIS10 :1; 01609 uint16_t X_DIS11 :1; 01610 uint16_t X_DIS12 :1; 01611 uint16_t Y_DIS9 :1; 01612 uint16_t Y_DIS10 :1; 01613 uint16_t Y_DIS11 :1; 01614 uint16_t Y_DIS12 :1; 01615 uint16_t ST_DIS1 :1; 01616 uint16_t ST_DIS2 :1; 01617 uint16_t ST_WDF :1; 01618 uint16_t ST_BSY :1; 01619 uint16_t ST_0 :1; 01620 uint16_t ST_EOP :1; 01621 uint16_t ST_TST :1; 01622 uint16_t ST_TFF :1; 01623 } Bits; 01624 struct { 01625 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01626 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01627 } MergedBits; 01628 } PROG_DISXY912; 01629 01630 typedef union { 01631 uint16_t word; 01632 struct { 01633 uint16_t ain1_current0 :1; 01634 uint16_t ain1_current1 :1; 01635 uint16_t ain1_current2 :1; 01636 uint16_t ain1_current3 :1; 01637 uint16_t ain2_current0 :1; 01638 uint16_t ain2_current1 :1; 01639 uint16_t ain2_current2 :1; 01640 uint16_t ain2_current3 :1; 01641 uint16_t ST_DIS1 :1; 01642 uint16_t ST_DIS2 :1; 01643 uint16_t ST_WDF :1; 01644 uint16_t ST_BSY :1; 01645 uint16_t ST_0 :1; 01646 uint16_t ST_EOP :1; 01647 uint16_t ST_TST :1; 01648 uint16_t ST_TFF :1; 01649 } Bits; 01650 struct { 01651 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01652 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01653 } MergedBits; 01654 } PROG_AIN12; 01655 01656 typedef union { 01657 uint16_t word; 01658 struct { 01659 uint16_t ain3_current0 :1; 01660 uint16_t ain3_current1 :1; 01661 uint16_t ain3_current2 :1; 01662 uint16_t ain3_current3 :1; 01663 uint16_t ain4_current0 :1; 01664 uint16_t ain4_current1 :1; 01665 uint16_t ain4_current2 :1; 01666 uint16_t ain4_current3 :1; 01667 uint16_t ST_DIS1 :1; 01668 uint16_t ST_DIS2 :1; 01669 uint16_t ST_WDF :1; 01670 uint16_t ST_BSY :1; 01671 uint16_t ST_0 :1; 01672 uint16_t ST_EOP :1; 01673 uint16_t ST_TST :1; 01674 uint16_t ST_TFF :1; 01675 } Bits; 01676 struct { 01677 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01678 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01679 } MergedBits; 01680 } PROG_AIN34; 01681 01682 typedef union { 01683 uint16_t word; 01684 struct { 01685 uint16_t ain5_current0 :1; 01686 uint16_t ain5_current1 :1; 01687 uint16_t ain5_current2 :1; 01688 uint16_t ain5_current3 :1; 01689 uint16_t ain6_current0 :1; 01690 uint16_t ain6_current1 :1; 01691 uint16_t ain6_current2 :1; 01692 uint16_t ain6_current3 :1; 01693 uint16_t ST_DIS1 :1; 01694 uint16_t ST_DIS2 :1; 01695 uint16_t ST_WDF :1; 01696 uint16_t ST_BSY :1; 01697 uint16_t ST_0 :1; 01698 uint16_t ST_EOP :1; 01699 uint16_t ST_TST :1; 01700 uint16_t ST_TFF :1; 01701 } Bits; 01702 struct { 01703 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01704 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01705 } MergedBits; 01706 } PROG_AIN56; 01707 01708 01709 typedef union { 01710 uint16_t word; 01711 struct { 01712 uint16_t aio1_wl_current0 :1; 01713 uint16_t aio1_wl_current1 :1; 01714 uint16_t aio1_wl_current2 :1; 01715 uint16_t aio1_wl_current3 :1; 01716 uint16_t aio2_wl_current0 :1; 01717 uint16_t aio2_wl_current1 :1; 01718 uint16_t aio2_wl_current2 :1; 01719 uint16_t aio2_wl_current3 :1; 01720 uint16_t ST_DIS1 :1; 01721 uint16_t ST_DIS2 :1; 01722 uint16_t ST_WDF :1; 01723 uint16_t ST_BSY :1; 01724 uint16_t ST_0 :1; 01725 uint16_t ST_EOP :1; 01726 uint16_t ST_TST :1; 01727 uint16_t ST_TFF :1; 01728 } Bits; 01729 struct { 01730 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01731 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01732 } MergedBits; 01733 } PROG_AIOWL; 01734 01735 typedef union { 01736 uint16_t word; 01737 struct { 01738 uint16_t aio_10 :1; 01739 uint16_t aio_11 :1; 01740 uint16_t aio_20 :1; 01741 uint16_t aio_21 :1; 01742 uint16_t Bit4 :1; 01743 uint16_t Bit5 :1; 01744 uint16_t Bit6 :1; 01745 uint16_t Bit7 :1; 01746 uint16_t ST_DIS1 :1; 01747 uint16_t ST_DIS2 :1; 01748 uint16_t ST_WDF :1; 01749 uint16_t ST_BSY :1; 01750 uint16_t ST_0 :1; 01751 uint16_t ST_EOP :1; 01752 uint16_t ST_TST :1; 01753 uint16_t ST_TFF :1; 01754 } Bits; 01755 struct { 01756 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01757 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01758 } MergedBits; 01759 } READ_AIO_STATUS; 01760 01761 typedef union { 01762 uint16_t word; 01763 struct { 01764 uint16_t ufs_threshold0 :1; 01765 uint16_t ufs_threshold1 :1; 01766 uint16_t ufs_threshold2 :1; 01767 uint16_t ufs_threshold3 :1; 01768 uint16_t ufs_threshold4 :1; 01769 uint16_t ufs_threshold5 :1; 01770 uint16_t sample0 :1; 01771 uint16_t sample1 :1; 01772 uint16_t ST_DIS1 :1; 01773 uint16_t ST_DIS2 :1; 01774 uint16_t ST_WDF :1; 01775 uint16_t ST_BSY :1; 01776 uint16_t ST_0 :1; 01777 uint16_t ST_EOP :1; 01778 uint16_t ST_TST :1; 01779 uint16_t ST_TFF :1; 01780 } Bits; 01781 struct { 01782 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01783 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01784 } MergedBits; 01785 } PROG_UFSTHRES; 01786 01787 typedef union { 01788 uint16_t word; 01789 struct { 01790 uint16_t pas_threshold0 :1; 01791 uint16_t pas_threshold1 :1; 01792 uint16_t pas_threshold2 :1; 01793 uint16_t pas_threshold3 :1; 01794 uint16_t pas_threshold4 :1; 01795 uint16_t pas_threshold5 :1; 01796 uint16_t sample0 :1; 01797 uint16_t sample1 :1; 01798 uint16_t ST_DIS1 :1; 01799 uint16_t ST_DIS2 :1; 01800 uint16_t ST_WDF :1; 01801 uint16_t ST_BSY :1; 01802 uint16_t ST_0 :1; 01803 uint16_t ST_EOP :1; 01804 uint16_t ST_TST :1; 01805 uint16_t ST_TFF :1; 01806 } Bits; 01807 struct { 01808 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01809 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01810 } MergedBits; 01811 } PROG_PASTHRES; 01812 01813 typedef union { 01814 uint16_t word; 01815 struct { 01816 uint16_t pres_threshold0 :1; 01817 uint16_t pres_threshold1 :1; 01818 uint16_t pres_threshold2 :1; 01819 uint16_t pres_threshold3 :1; 01820 uint16_t pres_threshold4 :1; 01821 uint16_t pres_threshold5 :1; 01822 uint16_t sample0 :1; 01823 uint16_t sample1 :1; 01824 uint16_t ST_DIS1 :1; 01825 uint16_t ST_DIS2 :1; 01826 uint16_t ST_WDF :1; 01827 uint16_t ST_BSY :1; 01828 uint16_t ST_0 :1; 01829 uint16_t ST_EOP :1; 01830 uint16_t ST_TST :1; 01831 uint16_t ST_TFF :1; 01832 } Bits; 01833 struct { 01834 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01835 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01836 } MergedBits; 01837 } PROG_PRESTHRES; 01838 01839 typedef union { 01840 uint16_t word; 01841 struct { 01842 uint16_t roll_threshold0 :1; 01843 uint16_t roll_threshold1 :1; 01844 uint16_t roll_threshold2 :1; 01845 uint16_t roll_threshold3 :1; 01846 uint16_t roll_threshold4 :1; 01847 uint16_t roll_threshold5 :1; 01848 uint16_t r_sample0 :1; 01849 uint16_t r_sample1 :1; 01850 uint16_t ST_DIS1 :1; 01851 uint16_t ST_DIS2 :1; 01852 uint16_t ST_WDF :1; 01853 uint16_t ST_BSY :1; 01854 uint16_t ST_0 :1; 01855 uint16_t ST_EOP :1; 01856 uint16_t ST_TST :1; 01857 uint16_t ST_TFF :1; 01858 } Bits; 01859 struct { 01860 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01861 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01862 } MergedBits; 01863 } PROG_ROLLTHRES; 01864 01865 typedef union { 01866 uint16_t word; 01867 struct { 01868 uint16_t x_threshold0 :1; 01869 uint16_t x_threshold1 :1; 01870 uint16_t x_threshold2 :1; 01871 uint16_t x_threshold3 :1; 01872 uint16_t x_threshold4 :1; 01873 uint16_t x_threshold5 :1; 01874 uint16_t sample0 :1; 01875 uint16_t sample1 :1; 01876 uint16_t ST_DIS1 :1; 01877 uint16_t ST_DIS2 :1; 01878 uint16_t ST_WDF :1; 01879 uint16_t ST_BSY :1; 01880 uint16_t ST_0 :1; 01881 uint16_t ST_EOP :1; 01882 uint16_t ST_TST :1; 01883 uint16_t ST_TFF :1; 01884 } Bits; 01885 struct { 01886 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01887 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01888 } MergedBits; 01889 } PROG_XTHRES; 01890 01891 typedef union { 01892 uint16_t word; 01893 struct { 01894 uint16_t y_threshold0 :1; 01895 uint16_t y_threshold1 :1; 01896 uint16_t y_threshold2 :1; 01897 uint16_t y_threshold3 :1; 01898 uint16_t y_threshold4 :1; 01899 uint16_t y_threshold5 :1; 01900 uint16_t sample0 :1; 01901 uint16_t sample1 :1; 01902 uint16_t ST_DIS1 :1; 01903 uint16_t ST_DIS2 :1; 01904 uint16_t ST_WDF :1; 01905 uint16_t ST_BSY :1; 01906 uint16_t ST_0 :1; 01907 uint16_t ST_EOP :1; 01908 uint16_t ST_TST :1; 01909 uint16_t ST_TFF :1; 01910 } Bits; 01911 struct { 01912 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01913 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01914 } MergedBits; 01915 } PROG_YTHRES; 01916 01917 01918 01919 01920 01921 typedef union { 01922 uint16_t word; 01923 struct { 01924 uint16_t SW_OFF :1; 01925 uint16_t SW_SMPL1 :1; 01926 uint16_t SW_SMPL2 :1; 01927 uint16_t SW_EN :1; 01928 uint16_t AIO_WL :1; 01929 uint16_t PLP_45_0 :1; 01930 uint16_t PLP_45_1 :1; 01931 uint16_t WD_DIS :1; 01932 uint16_t ST_DIS1 :1; 01933 uint16_t ST_DIS2 :1; 01934 uint16_t ST_WDF :1; 01935 uint16_t ST_BSY :1; 01936 uint16_t ST_0 :1; 01937 uint16_t ST_EOP :1; 01938 uint16_t ST_TST :1; 01939 uint16_t ST_TFF :1; 01940 } Bits; 01941 struct { 01942 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01943 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01944 } MergedBits; 01945 } PROG_GEN; 01946 01947 typedef union { 01948 uint16_t word; 01949 struct { 01950 uint16_t upper_threshold0 :1; 01951 uint16_t upper_threshold1 :1; 01952 uint16_t upper_threshold2 :1; 01953 uint16_t upper_threshold3 :1; 01954 uint16_t upper_threshold4 :1; 01955 uint16_t upper_threshold5 :1; 01956 uint16_t upper_threshold6 :1; 01957 uint16_t upper_threshold7 :1; 01958 uint16_t ST_DIS1 :1; 01959 uint16_t ST_DIS2 :1; 01960 uint16_t ST_WDF :1; 01961 uint16_t ST_BSY :1; 01962 uint16_t ST_0 :1; 01963 uint16_t ST_EOP :1; 01964 uint16_t ST_TST :1; 01965 uint16_t ST_TFF :1; 01966 } Bits; 01967 struct { 01968 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01969 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01970 } MergedBits; 01971 } PROG_UPTHRES; 01972 01973 typedef union { 01974 uint16_t word; 01975 struct { 01976 uint16_t lower_threshold0 :1; 01977 uint16_t lower_threshold1 :1; 01978 uint16_t lower_threshold2 :1; 01979 uint16_t lower_threshold3 :1; 01980 uint16_t lower_threshold4 :1; 01981 uint16_t lower_threshold5 :1; 01982 uint16_t lower_threshold6 :1; 01983 uint16_t lower_threshold7 :1; 01984 uint16_t ST_DIS1 :1; 01985 uint16_t ST_DIS2 :1; 01986 uint16_t ST_WDF :1; 01987 uint16_t ST_BSY :1; 01988 uint16_t ST_0 :1; 01989 uint16_t ST_EOP :1; 01990 uint16_t ST_TST :1; 01991 uint16_t ST_TFF :1; 01992 } Bits; 01993 struct { 01994 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 01995 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 01996 } MergedBits; 01997 } PROG_LOWTHRES; 01998 01999 typedef union { 02000 uint16_t word; 02001 struct { 02002 uint16_t mm5_sid_acc_10 :1; 02003 uint16_t mm5_sid_acc_11 :1; 02004 uint16_t mm5_sid_acc_12 :1; 02005 uint16_t mm5_sid_acc_20 :1; 02006 uint16_t mm5_sid_acc_21 :1; 02007 uint16_t mm5_sid_acc_22 :1; 02008 uint16_t Bit6 :1; 02009 uint16_t Bit7 :1; 02010 uint16_t ST_DIS1 :1; 02011 uint16_t ST_DIS2 :1; 02012 uint16_t ST_WDF :1; 02013 uint16_t ST_BSY :1; 02014 uint16_t ST_0 :1; 02015 uint16_t ST_EOP :1; 02016 uint16_t ST_TST :1; 02017 uint16_t ST_TFF :1; 02018 } Bits; 02019 struct { 02020 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02021 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02022 } MergedBits; 02023 } PROG_MM5SID; 02024 02025 typedef union { 02026 uint16_t word; 02027 struct { 02028 uint16_t DIS3 :1; 02029 uint16_t Bit1 :1; 02030 uint16_t PAR :1; 02031 uint16_t Bit3 :1; 02032 uint16_t SM :1; 02033 uint16_t Bit5 :1; 02034 uint16_t CM :1; 02035 uint16_t Bit7 :1; 02036 uint16_t ST_DIS1 :1; 02037 uint16_t ST_DIS2 :1; 02038 uint16_t ST_WDF :1; 02039 uint16_t ST_BSY :1; 02040 uint16_t ST_0 :1; 02041 uint16_t ST_EOP :1; 02042 uint16_t ST_TST :1; 02043 uint16_t ST_TFF :1; 02044 } Bits; 02045 struct { 02046 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02047 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02048 } MergedBits; 02049 } PROG_ENHSAFETY; 02050 02051 typedef union { 02052 uint16_t word; 02053 struct { 02054 uint16_t asyn :1; 02055 uint16_t S189k :1; 02056 uint16_t CRC1 :1; 02057 uint16_t slot0 :1; 02058 uint16_t slot1 :1; 02059 uint16_t S8Bit :1; 02060 uint16_t src :1; 02061 uint16_t Bit7 :1; 02062 uint16_t ST_DIS1 :1; 02063 uint16_t ST_DIS2 :1; 02064 uint16_t ST_WDF :1; 02065 uint16_t ST_BSY :1; 02066 uint16_t ST_0 :1; 02067 uint16_t ST_EOP :1; 02068 uint16_t ST_TST :1; 02069 uint16_t ST_TFF :1; 02070 } Bits; 02071 struct { 02072 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02073 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02074 } MergedBits; 02075 } PROG_PSI1LINE; 02076 02077 typedef union { 02078 uint16_t word; 02079 struct { 02080 uint16_t asyn :1; 02081 uint16_t S189k :1; 02082 uint16_t CRC1 :1; 02083 uint16_t slot0 :1; 02084 uint16_t slot1 :1; 02085 uint16_t S8Bit :1; 02086 uint16_t src :1; 02087 uint16_t Bit7 :1; 02088 uint16_t ST_DIS1 :1; 02089 uint16_t ST_DIS2 :1; 02090 uint16_t ST_WDF :1; 02091 uint16_t ST_BSY :1; 02092 uint16_t ST_0 :1; 02093 uint16_t ST_EOP :1; 02094 uint16_t ST_TST :1; 02095 uint16_t ST_TFF :1; 02096 } Bits; 02097 struct { 02098 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02099 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02100 } MergedBits; 02101 } PROG_PSI2LINE; 02102 02103 typedef union { 02104 uint16_t word; 02105 struct { 02106 uint16_t asyn :1; 02107 uint16_t S189k :1; 02108 uint16_t CRC1 :1; 02109 uint16_t slot0 :1; 02110 uint16_t slot1 :1; 02111 uint16_t S8Bit :1; 02112 uint16_t src :1; 02113 uint16_t Bit7 :1; 02114 uint16_t Status0 :1; 02115 uint16_t Status1 :1; 02116 uint16_t Status2 :1; 02117 uint16_t Status3 :1; 02118 uint16_t Status4 :1; 02119 uint16_t Status5 :1; 02120 uint16_t Status6 :1; 02121 uint16_t Status7 :1; 02122 } Bits; 02123 struct { 02124 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02125 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02126 } MergedBits; 02127 } PROG_PSI3LINE; 02128 02129 typedef union { 02130 uint16_t word; 02131 struct { 02132 uint16_t asyn :1; 02133 uint16_t S189k :1; 02134 uint16_t CRC1 :1; 02135 uint16_t slot0 :1; 02136 uint16_t slot1 :1; 02137 uint16_t S8Bit :1; 02138 uint16_t src :1; 02139 uint16_t Bit7 :1; 02140 uint16_t ST_DIS1 :1; 02141 uint16_t ST_DIS2 :1; 02142 uint16_t ST_WDF :1; 02143 uint16_t ST_BSY :1; 02144 uint16_t ST_0 :1; 02145 uint16_t ST_EOP :1; 02146 uint16_t ST_TST :1; 02147 uint16_t ST_TFF :1; 02148 } Bits; 02149 struct { 02150 uint8_t Data :8; //Different from 32Bits V1 QE, same as 8Bits QE 02151 uint8_t Status :8; //Different from 32Bits V1 QE, same as 8Bits QE 02152 } MergedBits; 02153 } PROG_PSI4LINE; 02154 02155 #endif //MY_TYPES_H 02156 02157 02158 02159 02160 02161
1.7.5.1 
